1. Field of the Invention
The present invention relates to a semiconductor multi-project or multi-product (MP) wafer process, and in particular, to a semiconductor MP wafer process with lower non-recurring engineering (NRE) prototyping or production manufacturing costs, a shorter cycle-time and more flexible semiconductor manufacturing or IC product mass production service.
2. Description of the Prior Art
As semiconductor technology scaling down and increasing in complexity, the NRE of new mask sets and wafers required to fabricate devices has been increasing significantly in complexity, number, and overall cost. For those fabless IC companies, the financial barrier of semiconductor IP/Lib design, IC prototyping or even small volume production becomes prohibitively higher for coming nano-meter (nm) scale technologies. One solution of easing the NRE costs offered by semiconductor foundry suppliers is to provide a multi-project wafer with a mask-shuttle. Using a mask-shuttle multi-project wafer service, the foundry provider can share the initial NRE cost over multiple fabless customers, depending on number of shuttle seats required for their IC design prototyping purposes.
Having mask-shuttle services, IC designs or IP/Lib (macro) function unit are submitted for semiconductor design verification using either open (i.e., non-proprietary) or vendor proprietary IP/Library. IC designs are pooled into a common mask set and in a prototyping wafer lot. Then, semiconductor wafers run through the fabrication process at semiconductor foundry. The finished semiconductor chips (packaged or unpackaged) are returned to those foundry customers or users who submitted their IC designs or IP/Lib (macro) functional units for making the multi-project wafer.
The semiconductor IC industry has experienced rapid growth for decades. Technological advances in IC materials, process and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and fabricating ICs. Furthermore, while the IC industry has been getting matured, the various operations needed to produce an IC may be performed at different locations by a single company or by different companies that specialize in a particular area. For example, IC foundry fabricating processes that use a mask shuttle can create multi-project wafers for a single or multiple customers.
FIG. 8 illustrates a conventional multi-project wafer mask set incorporated with multiple process nodes. The mask set 800 includes a first layer mask 802, a second layer mask 804, a third layer mask 806, a fifth layer mask 812, a sixth layer mask 814, and an eighth layer mask 820 that are multiple technology node mask (MTM). The mask set 800 further includes a fourth layer mask 808 and 810, a seventh layer mask 816 and 818. The masks 802, 804, 806, 812, 814 and 820 are single technology node mask (STM). The mask set MTMs (808, 816) and (810, 812) each include a first and second pattern associated with a different technology node respectively (for instance, 65 nm and 90 nm technology nodes). The fourth layer mask 808 and the seventh layer mask 816 are STMs and include the first pattern (e.g. 65 nm technology node) and the fourth layer mask 810 and the seventh layer mask 818 are STMs and include the second pattern (e.g. 90 nm technology node). The mask set 800 is used to fabricate a device including the first pattern, and a device including the second pattern.